**Small Signal Model of FET:**

The Small Signal Model of FET which consists of Low Frequency Small Signal Model for FET and High Frequency Model for FET.

**Low Frequency Model:** In a FET, instantaneous drain current i_{D} is a function of the instantaneous gate-source voltage v_{GS} and instantaneous drain-source voltage v_{DS} and is, therefore, expressed as

If both the gate and drain voltages are varied, the change in drain current is given approximately by the first two terms in the Taylor’s series expansion of Eq. (13.32) or

Using the conventional small signal notations, Δi_{D}, Δv_{GS} and Δv_{DS} may be replaced respectively by time varying components i_{d}, v_{gs} and v_{ds}. Now Eq. (13.33) becomes

Parameter g_{m} is the mutual conductance, or transconductance

The reciprocal of r_{d} is the drain conductance g_{d}.

Circuit shown in Fig. 13.32 is made satisfying Eq. (13.34) giving the incremental drain current i_{d} in form of g_{m}, r_{d}, v_{gs} and v_{ds}. This circuit forms the low frequency Small Signal Model of FET: This model consists of one dependent current generator whose current g_{m}v_{gs} is proportional to the time varying gate source voltage v_{gs} and proportionality constant is the transconductance g_{m}.

The arrow points from drain to source to indicate a phase change of 180° (or phase reversal) between output and input voltages as will occur in actual operation. In low frequency model, as the gate is reverse biased, the gate current becomes zero. So, in low frequency model, gate to source junction is represented by an open circuit and no current is drawn by the input terminal of the FET. The reason is that input resistance, (gate-to-source resistance) is very large. The output resistance is represented by the resistance r_{d} (resistance from drain to source). If r_{d} is sufficiently large as compared to those of other circuit elements, this is ignored. Now the equivalent circuit becomes simply a current source whose magnitude is controlled by v_{gs} and g_{m}—clearly a voltage controlled current source.

Small Signal Model of FET for sinusoidal input voltage of rms value V_{gs} may be drawn, as shown in Fig. 13.33 where v_{gs}, i_{d}, v_{ds} have been replaced respectively by rms values V_{gs}, I_{d} and V_{ds}. The voltage-controlled current source (g_{m} V_{gs}) can be replaced by equivalent voltage-controlled voltage source (μV_{gs}) as depicted in Fig. 13.34.

Now the equivalent circuit consists of a voltage source (μV_{gs}) in series with a drain resistance r_{d}. Here μ is the amplification factor of the FET and is equal to the product of transconductance g_{m} and drain resistance r_{d} i.e., μ = g_{m}r_{d}.

**Comparison of Low Frequency Models of FET and BJT:**

- Both FET and BJT models have a dependent current generator in the output circuit.
- In FET models, the generator current is proportional to the input voltage V
_{gs }while in BJT models, the generator current is proportional to the input current. - In FET models input impedance is very high (theoretically infinite at low frequencies) while in common emitter BJT model the input impedance is of the order of 800 Ω.
- In FET, there is no feedback from output (drain) to the input (source) while in BJT models it is. Thus it can be safely said that at low frequencies, FET forms a more ideal amplifier than BJT amplifier.

**High Frequency Model: **At low frequency, reactance offered by interelectrode capacitance is very large and, therefore, interelectrode capacitances do not appear in low frequency equivalent circuit. At higher frequencies device capacitances between terminals cause reduction in amplifier gain as capacitive impedance decreases with the increase in supply frequency. Such circuit capacitances resulted in due to device construction or stray wiring are shown as connected with dashed lines in the circuit of Fig. 13.35 to indicate that they are not capacitances that are connected into the circuit intentionally but arise as a result of the circuit and device construction.

Figure 13.36 depicts the high frequency model of the FET which is identical with Fig. 13.32 except that the capacitances between the gate-source and gate-drain nodes are shown in the figure. The capacitor C_{gs} represents the barrier capacitance between gate and source, and C_{gd} is the barrier capacitance between gate and drain. The element C_{ds} represents the drain to source capacitance of the channel. Because of these internal capacitances feedback exists between the input and output circuits of the FET and voltage amplification drops drastically with increase in frequency.