**Foster Seeley Detector – Circuit Diagram, Working and its Phasor Diagram:**

The circuit diagram of the Foster Seeley detector is shown in Fig. 22.54. This Foster Seeley Detector circuit consists of an inductively coupled double tuned circuit in which both primary and secondary coils are tuned to the same frequency (intermediate frequency).

The centre of the secondary coil is connected to the top of the primary (collector end) through a capacitor C. This capacitor C performs the following functions:

- It blocks the dc from primary to secondary.
- It couples the signal frequency from primary to centre tapping of secondary.

The primary voltage V_{3} (i.e., the signal voltage) thus appears across the inductor L. Nearly entire voltage V_{3} appears across inductor L except a small drop across the capacitor C. However, by a suitable choice of C and L, the voltage drop across the capacitor C can be made negligible.

The centre tapping of the secondary coil has an equal and opposite voltage across each half winding. Hence V_{1} and V_{2} are equal in magnitude but opposite in phase. The radio frequency voltages V_{a1} and V_{a2} applied to the diodes D_{1} and D_{2} are expressed as

Voltage V_{a1} and V_{a2} depend upon the phase relations between V_{1}, V_{2} and V_{3}. The phasor diagrams of Foster Seeley Detector for different frequencies have been shown in Fig. 22.55. The phasors V_{1} and V_{2} are always equal in magnitude but in phase opposition. However, the phase position of V_{1} and V_{2} relative to V_{3} would depend upon the tuned secondary coil at the resonance or off the resonance as discussed below :

**1. At Resonance:** When an input voltage has a frequency equal to the resonant frequency f_{if} of the tuned secondary, V_{3} is in phase quadrature (90° out of phase) with V_{1} and V_{2}. This has been indicated in Fig. 22.55 (a). The resultant voltages V_{a1} and V_{a2} are equal in magnitude.

**2. Off Resonance:** When the input voltage is off the resonant frequency f_{if} of the tuned secondary, the phase position of V_{1} and V_{2} relative to V_{3} will be different from 90°. Let Q_{s} be the quality factor of tuned secondary coil. When an input signal frequency exceeds the resonant frequency f_{if} by an amount f_{if}/2Q_{s} the phase difference between V_{3} and V_{1} is 45° as shown in Fig. 22.55 (b). Because V_{2} is in phase opposition of V_{1}, the phase difference between V_{3} and V_{2} is 135°. The phasor diagram shown in Fig. 22.55 (b) reveals that V_{a1} is reduced whereas V_{a2} is increased. The situation is reversed when the input voltage has a frequency below f_{if }which is evident from the phasor diagram shown in Fig. 22.55 (c). Thus the magnitude of the voltages V_{a1} and V_{a2} will vary with the instantaneous frequency f in the manner shown in Fig. 22.56.

The RF voltages V_{a1} and V_{a2} are separately rectified by the diodes D_{1} and D_{2} respect^{i}vely to provide voltages V_{out1} and V_{out2}. The RF components are bypassed by the capacitors leaving only modulating frequency component and a dc term. The voltages V_{out1} and V_{out2} then represent the amplitude variations of voltages V_{a1} and V_{a2}_{ }respectively. The diodes are so arranged that the output voltage V_{out} is equal to the arithmetic difference | V_{out2} | – | V_{out1 }|.

Thus, the output voltage V_{out} will vary with instantaneous frequency in accordance with the difference | V_{out2} | – | V_{out1 }|, as shown by the dotted curve in Fig. 22.56 (b). This allotted curve is known as **discriminator characteristic** in Fig. 22.56.