Parallel Adder and Subtractor

Parallel Adder and Subtractor: Parallel Adder and Subtractor which consists of three categories, namely,    n Bit Parallel Adder,Binary Parallel Adder and n Bit Parallel Subtractor. n Bit Parallel Adder: We have seen, a single full-adder is capable of adding two one-bit numbers and an input carry. In order to add binary numbers with more […]

Half Subtractor and Full Subtractor Circuit

Half Subtractor and Full Subtractor Circuit: Subtractor are divided into two categories namely, half subtractor and full subtractor circuit. Half Subtractor Circuit: The Half Subtractor Circuit consists of four possible elementary operations, namely, In all operations, each subtrahend bit is subtracted from the minuend bit. In case of second operation the minuend bit is smaller […]

Half Adder and Full Adder Circuit

Half Adder and Full Adder Circuit: Adders are divided into two categories namely, half adder and full adder circuit. Half Adder Circuit: The Half Adder Circuit operation needs two binary inputs : augend and addend bits; and two binary outputs : sum and carry. The half adder truth table shown in 3.6 gives the relation […]

Control Signals of 8085

Control Signals of 8085: The 8085 Microprocessor provides RD and WR signals to initiate read or write cycle. Because these Control Signals of 8085 are used both for reading/writing memory and for reading/writing an input device, it is necessary to generate separate read and write signals for memory and I/O devices. The 8085 provides IO/M […]

Power on Reset Circuit of 8085

Power on Reset Circuit in 8051: On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction from address 0000H. For proper reset operation reset signal must be held low for at least 3 clock cycles. The power-on Reset Circuit of 8085 can be used to ensure execution of first […]

Latching Circuit

Latching Circuit: We know that AD0 to AD7 lines are multiplexed and the lower half of address (A0 – A7) is available only during T1 of the machine cycle. This lower half of address is also necessary during T2 and T3 of machine cycle to access specific location in memory or I/O port. This means […]

Voltage and Current Divider Rule

Voltage and Current Divider Rule: Voltage and Current Divider Rule is explained by two conditions, namely Voltage Division in Series Circuit of Resistors Current Division in Parallel Circuit of Resistors Voltage Division in Series Circuit of Resistors: Consider a series circuit of two resistors R1 and R2 connected to source of V volts is shown […]

Routh Criterion

Routh Criterion: Routh Criterion – The locations of the poles gives us an idea about stability of the active network. Consider the denominator polynomial To get a stable system, all the roots must have negative real parts. There should not be any positive or zero real parts. This condition is not sufficient. Let us consider […]

Stability Criterion in Network Function

Stability Criterion in Network Function: Stability Criterion – Passive networks are said to be stable only when all the poles lie in the left half of the s-plane. Active networks (containing controlled sources) are not always stable. Consider transformed active network shown in Fig. 14.13. By applying Millman Theorem, we get From the above transformed […]

Poles and Zeros of Time Domain Response

Poles and Zeros of Time Domain Response: For the given network function, a pole zero plot can be drawn which gives useful information regarding the critical frequencies. The Poles and Zeros of Time Domain Response can also be obtained from pole zero plot of a network function. Consider an array of poles shown in Fig. […]