**JFET Biasing Circuits:**

**Use of Plus/Minus Supplies –** When plus/minus supply voltages are to be used with a JFET Biasing Circuits, the gate terminal is usually grounded via R_{G}, as illustrated in Fig. 10-40(a). In this case, the circuit is essentially a voltage divider bias circuit with the gate bias voltage equal to the level of the negative supply voltage, (V_{G} = V_{SS}). The (reverse) gate-source bias voltage (-V_{GS}) makes the source terminal +V_{GS} above ground. So,

When the voltage levels are understood, the type of circuit in Fig. 10-40(a) can be designed using a procedure similar to that for a voltage divider bias circuit. I_{D(max)} is plotted on the maximum transfer characteristics, and V_{GS} is read from the horizontal axis V_{GS} can also be determined by substituting I_{D(max)}, I_{DSS(max)}, and V_{P(max)} into Eq. 10-8. Then, with the desired maximum voltage drops known, R_{D} and R_{S} are readily calculated. R_{G} is selected as 1 MΩ, or less, for the reasons already discussed.

Analysis procedure for this circuit is also like that for a voltage divider bias circuit. One point on the bias line is plotted on the transfer characteristics at V_{G} = V_{SS}, as shown on Fig. 10-40(b), and the bias line is drawn at the slope determined by R_{s}. As always, the bias line intersections with the maximum and minimum characteristics gives the I_{D(max)} and I_{D(min)} levels.

**Drain Feedback:**

The drain feedback JFET Biasing Circuits in Fig. 10-41 is essentially a voltage divider bias circuit. However, instead of V_{G} being derived from the supply voltage, the FET drain voltage (V_{D}) is divided by R_{1} and R_{2} to produce V_{G}. Modifying Eq. 10-7,

The circuit is designed for a particular level of V_{D} and I_{D}, and the voltage drop across R_{S} helps to stabilize I_{D}, as in other voltage divider bias circuits. The voltage drop across R_{D} also provides feedback that helps to correct changes in I_{D}. When I_{D} is greater than the design value, V_{RD} is increased, V_{D} is reduced, and thus V_{G} is lowered to drive I_{D} back toward its original level. The two feedback effects (V_{RD} changes and V_{RS} changes) tend to keep I_{D(min)} and I_{D(max) }closer than in an ordinary voltage divider JFET Biasing Circuits.

Design procedure for this circuit is the same as for voltage divider bias with the exception that the voltage drop across R_{1} is (V_{D} – V_{G}) instead of (V_{DD} – V_{G}). For circuit analysis a bias line should be drawn on the transfer characteristics, as always. This requires the equation relating V_{GS} and I_{D}.

**Constant Current Bias:**

As already discussed, the bias lines with the smallest slope give the closest levels of I_{D(min)} and I_{D(max)}. In the two circuits in Fig. 10-42 the bipolar transistor (Q_{2}) keeps the FET source current constant. Consequently, as illustrated in Fig. 10-43, the bias line is drawn horizontally on the transfer characteristics, showing I_{D(min)} = I_{D(max)}, with different V_{GS} levels.

Both circuits provide bias voltage V_{B} to the base of Q_{2}, to give,

The circuit in Fig. 10-42(a) uses voltage divider bias to derive V_{B} from V_{DD}, and in Fig. 10-42(b) V_{B} = V_{EE}. In both cases, the FET gate is connected to the base of Q_{2} via resistor R_{G}, and V_{GS} = -V_{CB}.

Design of each of the circuit in Fig. 10-42 simply involves selection of appropriate voltage and current levels and calculation of the resistors. The emitter resistor voltage drop (V_{E}) should typically be a minimum of 5 V, but satisfactory results can be obtained with 3 V. It can, of course, be much larger than 5 V, as would normally be the case in Fig. 10-42(b). In both circuits,

The level of V_{B} calculated in this way can be used to determine the ratio of R_{1} and R_{2} in Fig. 10-42(a). For the circuit in Fig. 10-42(b), V_{EE} indicates the V_{B} and V_{E} levels.

The maximum V_{GS} level is determined by plotting I_{D} on the maximum transfer characteristic for the FET, and then reading V_{GS(max) }at I_{D}. Alternatively, V_{GS} can be calculated from Eq. 10-8. The source terminal voltage is more positive than the gate. The equation for V_{S},

Analysis of each of the circuits in Fig. 10-42 is very simple. Once V_{B} is determined, I_{D} is calculated using Eq. 10-17. V_{GS(max) }and V_{GS(min) }are found by drawing the bias line for I_{D} on the transfer characteristics, or by substituting I_{D}, V_{P}, and I_{DSS} into Eq. 10-8.