JFET Temperature Effects:

The JFET, like other solid state devices, is subject to the JFET Temperature Effects. However, it is possible to bias the JFET such that it will exhibit a zero temperature coefficient i.e. drain current I_D will be independent of temperature. This is explained below :

There are two primary mechanisms underlying the temperature sensitivity of the conductivity of a JFET channel.

1. Decrease in the depletion region width at the channel-gate P-N junction with the increase in temperature. This results in increase of channel thickness.
2. Decrease in carrier mobility with the increase in temperature.

Increase in channel thickness with the increase in temperature makes drain current I_D to increase. Another way of looking into the situation is to note that V_{GS (OFF)} increases in magnitude with the increase in temperature. So far a fixed value of V_GS, I_D will increase with the temperature. V_{GS (OFF)} [V_P] has a positive temperature coefficient of about 2.2 mV/°C.

The second factor [decrease in carrier mobility with the increase in temperature] makes the channel conductivity to decrease with the increase in temperature. The result is that drain current I_D decreases (assuming V_DS constant) with the increase in temperature. Thus we see that I_DSS tends to fall as the temperature rises.

Thus we have two distinct mechanisms affecting drain current I_D as a function of temperature. Carrier mobility gives I_D a negative temperature coefficient while the effect of V_{GS (OFF)} is to give I_D a positive temperature coefficient. Since both of these mechanisms occur simultaneously, it is possible to bias the JFET so as to exhibit a zero temperature coefficient. Thus JFETs have better thermal stability.

The value of V_GS that will give drain current I_D for both N­ and P-channel JFETs a zero temperature coefficient is given as