Biasing FET Switching Circuits:

JFET Switching – A Biasing FET Switching Circuits is normally in an off state with zero drain current, or in an on state with a very small drain-source voltage. When the FET is off, there is a drain-source leakage current so small that it can almost always be neglected. When the device is on, the drain-source voltage drop depends on the channel resistance (r_DS(on)) and the drain current (I_D). 

Field effect transistors designed specifically for switching applications have very low channel resistances. For example, the 2N4856 has r_DS(on) = 25 Ω. With low I_D levels, r_DS(on) can be much smaller than the 0.2 V typical V_CE(sat) for a BJT. This is an important advantage of a FET switch over a BJT switch.

Direct-Coupled JFET Switching Circuit:

A direct-coupled Biasing FET Switching Circuits is shown in Fig. 10-54(a), and the circuit wave forms are illustrated in Fig. 10-54(b). When V_i = 0, the FET gate and source voltages are equal and there is no depletion region penetration into the channel. The output voltage is now V_o = V_DS(on), as expressed by Eq. 10-20. When V_i exceeds the FET pinch-off voltage, the device is switched off, and the output voltage goes to V_DD, as illustrated.

Assuming that V_DS(on) is very small, the drain current level is determined from,

Equation 10-21 can be used to determine R_D when V_DD and I_D are specified, or to calculate I_D when R_D is known. The I_D level can then be employed to determine V_DS(on). The lowest drain current that can be used must be very much greater than the specified drain-source leakage current for the device.

To switch the FET off, V_i should exceed the maximum pinch-off voltage. However, V_i must not be so large that the drain-gate voltage (V_DG = V_DD + V_i) approaches the breakdown voltage. A rule­-of-thumb is to select the input voltage 1 V larger than V_P(max).

The gate resistor (R_G) in the circuit in Fig. 10-54 is provided solely to limit any gate current in the event that the gate-source junctions become forward biased. The circuit might operate satisfactorily with R_G selected as 1 MΩ, however, high-value resistors can slow the switching speed of the circuit, so, quite small resistance values are often used for R_G.

Capacitor-Coupled JFET Switching Circuits:

Two capacitor-coupled Biasing FET Switching Circuits are shown in Fig. 10-55. The FET in Fig. 10-55(a) is normally-on because it has V_GS = 0, and the device in Fig. 10-55(b) is normally-off with -V_GS greater than the pinch-off voltage. In both circuits, the FET is switched on or off by a capacitor-coupled input pulse. The design procedure for these circuits uses the equations already discussed for the direct coupled Biasing FET Switching Circuits.

MOSFET Switching:

Figure 10-56 shows two capacitor-coupled MOSFET switching circuits. In Fig. 10-56(a), the FET is biased off because V_GS = 0. A positive-going input signal is required to turn the device on. The FET in Fig. 10-56(b) is biased on by the positive V_GS provided by R₁ and R₂. In this case, a negative-going input voltage must be applied to turn the FET off Equations 10-20 and 10-21 can be applied to these circuits to calculate I_D and V_DS(on). To turn the device on to a desired level of drain current, the transfer characteristics can be employed if they are available.