CMOS NAND Gate Circuit Diagram:

Fig. 3.3 shows CMOS NAND Gate Circuit Diagram 2-input NAND gate. It consists of two P-channel MOSFETs, Q₁ and Q₂, connected in parallel and two N-channel MOSFETs, Q₃ and Q₄ connected in series.

P-channel MOSFET is ON when its gate voltage is negative with respect to its source whereas N-channel MOSFET is ON when its gate voltage is positive with respect to its source

Fig. 3.3 (a) shows the equivalent switching circuit when both inputs are low. Here, the gates of both P-channel MOSFETs are negative with respect to their sources, since the sources are connected to +V_DD. Thus, Q₁ and Q₂ are both ON. Since the gate – to – source voltages of Q₃ and Q₄ (N-channel MOSFETs) are both 0V, those MOSFETs are OFF. The output is therefore connected to +V_DD (HIGH) through Q₁ and Q₂ and is disconnected from ground, as shown in the Fig. 3.3 (b).

Fig. 3.3 (c) shows the equivalent switching circuit when A = 0 and B = +V_DD. In this case, Q₁ is on because V_GS1 = −V_DD and Q₄ is ON because V_GS4 = +V_DD. MOSFETs Q₂ and Q₃ are off because their gate-to-source voltages are 0 V. Since Q₁ is ON and Q₃ is OFF, the output is connected to +V_DD and it is disconnected from ground. When A = +V_DD and B = 0V, the situation is similar (not shown) ; the output is connected to +V_DD through Q₂ and it is disconnected from ground because Q₄ is OFF. Finally, when both inputs are high (A = B = +V_DD), MOSFETs Q₁ and Q₂ are both OFF and Q₃ and Q₄ are both ON. Thus, the output is connected to the ground through Q₃ and Q₄ and it is disconnected from +V_DD.

The Table 3.2 summarizes the operation of 2-input CMOS Inverter NAND gate.