CMOS Inverter Circuit:
CMOS Inverter Circuit contain both NMOS and PMOS devices to speed the switching of capacitive loads. It consumes low power and can be operated at high voltages, resulting in improved noise immunity.
Fig. 3.1 shows the basic CMOS inverter circuit. It consists of two MOSFETs in series in such a way that the P-channel device has its source connected to +VDD (a positive voltage) and the N-channel device has its source connected to ground. The gates of the two devices are connected together as the common input and the drains are connected together as the common output.
When input is HIGH, the gate of Q1 (P-channel) is at 0V relative to the source of Q1 i.e. VGS1 = 0V. Thus, Q1 is OFF. On the other hand, the gate of Q2 (N-channel) is at +VDD relative to its source i.e. VGS2 = +VDD. Thus, Q2 is ON. This will produce Vout ≈ 0 V, as shown in the Fig. 3.2 (a).
When input is LOW, the gate of Q1 (P-channel) is at a negative potential relative to its source while Q2 has VGS = 0 V. Thus, Q1 is ON and Q2 is OFF. This produces output voltage approximately +VDD, as shown in the Fig. 3.2 (b).
Table 3.1 summarizes the operation of CMOS Inverter Truth Table
CMOS NAND Gate:
Fig. 3.3 shows CMOS Inverter Circuit 2-input NAND gate. It consists of two P-channel MOSFETs, Q1 and Q2, connected in parallel and two N-channel MOSFETs, Q3 and Q4 connected in series.
P-channel MOSFET is ON when its gate voltage is negative with respect to its source whereas N-channel MOSFET is ON when its gate voltage is positive with respect to its source
Fig. 3.3 (a) shows the equivalent switching circuit when both inputs are low. Here, the gates of both P-channel MOSFETs are negative with respect to their sources, since the sources are connected to +VDD. Thus, Q1 and Q2 are both ON. Since the gate – to – source voltages of Q3 and Q4 (N-channel MOSFETs) are both 0V, those MOSFETs are OFF. The output is therefore connected to +VDD (HIGH) through Q1 and Q2 and is disconnected from ground, as shown in the Fig. 3.3 (b). Fig. 3.3 (c) shows the equivalent switching circuit when A = 0 and B = +VDD. In this case, Q1 is on because VGS1 = −VDD and Q4 is ON because VGS4 = +VDD. MOSFETs Q2 and Q3 are off because their gate-to-source voltages are 0 V. Since Q1 is ON and Q3 is OFF, the output is connected to +VDD and it is disconnected from ground. When A = +VDD and B = 0V, the situation is similar (not shown) ; the output is connected to +VDD through Q2 and it is disconnected from ground because Q4 is OFF. Finally, when both inputs are high (A = B = +VDD), MOSFETs Q1 and Q2 are both OFF and Q3 and Q4 are both ON. Thus, the output is connected to the ground through Q3 and Q4 and it is disconnected from +VDD. The Table 3.2 summarizes the operation of 2-input CMOS Inverter NAND gate.
CMOS NOR Gate:
Fig. 3.4 shows 2-input CMOS NOR Gate Circuit. Here, P-channel MOSFETs Q1 and Q2 are connected in series and N-channel MOSFETs Q3 and Q4 are connected in parallel.
Like NAND circuit, this circuit can be analyzed by realizing that a LOW at any input turns ON its corresponding P-channel MOSFET and turns OFF its corresponding N-channel MOSFET, and vice versa for a HIGH input. This is illustrated in Fig. 3.4. The Table 3.3 summarizes the operation of 2 Input NOR Gate.
Operating Speed : Slower than TTL series. Approximately 25 to 100 ns depending on the subfamily of CMOS Inverter Circuit. It also depends on the power supply voltage.
Voltage Levels and Noise Margins : The voltage levels for CMOS Inverter Circuit varies according to their subfamilies. These are listed in Table 3.4. Noise margins in table are calculated as follows.
Fanout : The CMOS inputs have an extremely large resistance (1012Ω) that draws essentially no current from the signal source. Each CMOS input, however, typically presents a 5 pF load to ground as shown in the Fig. 3.5. This input capacitance limits the number of CMOS inputs that one CMOS output can drive.
The CMOS output has to charge and discharge the parallel combination of all the input capacitances. This charging and discharging time increases as we increase number of loads. Typically, each CMOS load increases the driving circuit’s propagation delay by 3 ns. Thus, fan-out for CMOS depends on the permissible maximum propagation delay. Typically, CMOS outputs are limited to a fan-out of 50 for low-frequency operation (≤ 1 MHz). Of course, for high-frequency operation the fan-out would have to be less.
Power Dissipation (PD) : The power dissipation of a CMOS IC is very low as long as it is in a dc condition. Unfortunately, power dissipation of CMOS IC increases in proportion to the frequency at which the circuits are switching states. For example, a CMOS NAND gate that has PD =10 nW under DC conditions will have PD = 0.1 mW at a frequency of 100 kHz, and 1 mW at 1 MHz.
When CMOS output switches from LOW to HIGH, a transient charging current has to be supplied to the load capacitance. Therefore, as the switching frequency increases, the average current drawn from VDD also increases, resulting increase in power dissipation.
Propagation Delay :The propagation delay in CMOS is the sum of delay due to internal capacitance and due to load capacitance. The delay due to internal capacitance is called the intrinsic propagation delay. The delay due to load capacitance can be approximated as follows :
tp(CL) ≈ 0.5 Ro CL seconds
Ro is the output resistance of the gate, and CL is the total load capacitance.
The Ro depends on the supply voltage and it can be approximated as
where Ios is the short circuit output current.
Unused Inputs : CMOS inputs should never be left disconnected. All CMOS inputs have to be tied either to a fixed voltage level (0V or VDD) or to another input. This rule applies even to the inputs of extra unused logic gates on a chip. An unused CMOS input is susceptible to noise and static charges that could easily bias both the P-and N-channel MOSFETs in the conductive state, resulting in increased power dissipation and possible overheating.
Static-charge Susceptibility (CMOS Hazards) : Every CMOS device is vulnerable to the building up of electrical charge on its insulated gate. Recall that the relationship between charge Q and voltage V on a capacitor having capacitance C is
V = Q/C
Since the input capacitance at the gate is usually quite small (a few picofarads), a relatively small amount of charge can create a large voltage which may be greater than the breakdown voltage of a MOS gate (typically 100 V).
The primary source of charge is “static” electricity, usually produced by handling and the motion of various kinds of plastics and textiles. The CMOS devices are protected against this static charge by on-chip diode-resistor network, as shown in the Fig. 3.6. These diodes are designed to turn ON and limit the size of the input voltage to well below any damaging value.
Latch-up : CMOS integrated circuits contain parasitic PNP and NPN transistors : transistors that exist because of the proximity of P and N materials embedded in the substrate. Their existence is not intentional but is unavoidable. Because of conducting paths between a pair of such transistors, a device can be triggered into a heavy conduction mode, known as latch-up. This heavy conduction mode, results large current flow which can destroy IC. Most CMOS circuits contain protective measures to prevent latch-up, but it can still occur if the manufacturers specified maximum ratings are exceeded.