**UJT Circuit Diagram:**

**UJT Circuit Diagram Operation : **The Unijunction transistor (UJT) consists of a bar of lightly-doped n-type silicon with a block of p-type material on one side, [see Fig. 19-39(a)].The end terminals of the bar are identified as Base 1 (B_{1}) and Base 2 (B_{2}), and the p-type block is named the emitter (E).

Figure 19-39(b) shows the UJT equivalent circuit. The resistance of the n-type silicon bar is represented as two resistors, r_{B1} from B_{1 }to point C, and r_{B2} from B_{2} to C, as illustrated. The sum of r_{B1} and and r_{B2} is identified as R_{BB}. The p-type emitter forms a pn-junction with the n-type silicon bar, and this junction is shown as a diode (D_{1}) in the equivalent circuit.

With a voltage V_{B1B2} applied as illustrated, the voltage at the junction r_{B1} and r_{B2} is,

Note that V_{1} is also the voltage at the cathode of the diode; point C in the equivalent circuit.

With the emitter terminal open-circuited, the resistor current is,

If the emitter terminal is grounded, the pn-junction is reverse biased and a small **emitter reverse current** (I_{E0}) flows.

Now consider what happens when the emitter voltage (V_{EB1}) is slowly increased from zero. When V_{EB1} equals V_{1} the emitter current is zero. (With equal voltage levels on each side of the diode, neither reverse nor forward current flows.) A further increase in V_{EB1} forward biases the pn-junction and causes a forward current (I_{E}) to flow from the p-type emitter into the n-type silicon bar. When this occurs, charge carriers are injected into the r_{B1} region. The resistance of the semiconductor material is dependent on doping, so the additional charge carriers cause the resistance of the r_{B1} region to rapidly decrease. The decrease in resistance reduces the voltage drop across r_{B1}, and so the pn-junction is more heavily forward biased. This in turn results in a greater emitter current, and more charge carriers that further reduce the resistance of the r_{B1} region. (The process is termed **regenerative**) The input voltage is pulled down, and the emitter current (I_{E}) is increased to a limit determined by the V_{EB1} source resistance. The device remains in this on condition until the emitter input is open-circuited, or until I_{E} is reduced to a very low level.

The circuit symbol for a UJT Circuit Diagram is shown in Fig. 19-39(c). As always, the arrowhead points in the conventional current direction for a forward-biased junction. In this case it points from the p-type emitter to the n-type bar.

**UJT Characteristics:**

A plot of emitter voltage V_{EB1} versus emitter current I_{E} gives the UJT emitter characteristics. Refer to the UJT Circuit Diagram terminal voltages and currents identified in Fig. 19-40(a) and to the equivalent circuit in Fig. 19-39(b). Note that when V_{B1B2} = 0, I_{B2} = 0 and V_{1} =0. If V_{EB1} is now increased from zero, the resultant plot of V_{EB1} and I_{E} is simply the characteristic of a forward-biased diode with some series resistance. This is the characteristic for I_{B2} = 0 in Fig. 19-40(b).

When V_{B1B2} is 20 V the level of V_{1} (Fig. 19-39(b)] might be around 15 V, depending on the resistances of r_{B1} and r_{B2}. With V_{B1B2} = 20 V and V_{E} = 0, the emitter junction is reverse biased and the emitter reverse current I_{E0} flows, as shown at point 1 on the V_{B1B2} = 20 V characteristic in Fig. 19-40(b). Increasing the level of V_{EB1} until it equals V_{1} gives I_{E} = 0; point 2 on the characteristic. Further increase in V_{EB1} forward biases the emitter junction, and this gives the peak point on the characteristic (point 3). At the peak point, V_{EB1} is identified as the peak voltage (V_{P}) and I_{E} is termed the peak current (I_{p}).

Up until the peak point the UJT is said to be operating in the cutoff region of its characteristics. When V_{EB1} arrives at the peak voltage, charges carriers are injected from the emitter to decrease the resistance of r_{B1}, as already explained. The device enters the negative resistance region, r_{B1} falls rapidly to a **saturation resistance** (r_{s}), and V_{EB1} falls to the valley voltage (V_{V}), [point 4 on the characteristic in Fig. 19-40(b)]. I_{E} also increases to the valley current (I_{V}) at this time. Further increase in I_{E} causes the device to enter the saturation region where V_{E} equals the sum of V_{D} and I_{E}r_{S}.

Starting with V_{B1B2 }lower than 20 V gives a lower peak point voltage and a different characteristic. Thus, using various levels of V_{B1B2}, a family of V_{EB1}/I_{E} characteristics can be plotted for a given UJT, as shown in Fig. 19-40(c).

**UJT Packages:**

Two typical UJT packages with the terminal identified are shown in Fig 19-41. These are similar to low-power BJT packages.

**UJT Parameters:**

**Interbase Resistance (R _{BB}):** This is the sum of r

_{B1}and r

_{B2}when I

_{E}is zero. Consider Fig. 19-42 that shows a portion of the manufacturer’s data sheet for 2N4949 UJT. R

_{BB}is specified as 7 kÎ© typical, 4 kÎ© minimum, and 12 kÎ© maximum. The value of R

_{BB}, together with the maximum power dissipation P

_{D}, determine the maximum value of V

_{B1B2}that may be used. With I

_{E}= 0,

Like all other devices, the P_{D} of the UJT must be derated for increased temperature levels.

**Intrinsic Standoff Ratio (Î·):** The intrinsic standoff ratio is simply the ratio of r_{B1 }to R_{BB}. The peak point voltage is determined from Î·, the supply voltage, and the diode voltage drop;

**Emitter Saturation Voltage (V _{EB1(sat)}): **The emitter voltage when the UJT is operating in the saturation region of its characteristics; the minimum V

_{EB1}level. Because it is affected by the emitter current and the supply voltage, V

_{EB1(sat)}is specified for given I

_{E}and V

_{B1B2}levels.

**Peak Point Emitter Current (I _{P}): **I

_{P}is important as a lower limit to the emitter current. If the emitter voltage source resistance is so high that I

_{E}is not greater than I

_{P}the UJT will simply not trigger on. The maximum emitter voltage source resistance is,

**Valley Point Current (I _{V}):** I

_{V}is important in some circuits as an upper limit to the emitter current. If the emitter voltage source resistance is so low that I

_{E}is equal to or greater than I

_{V}, the UJT will remain on once it is triggered; it will not switch off. So, the minimum emitter voltage source resistance is,

**UJT Relaxation Oscillator:**

The relaxation oscillator circuit in Fig. 19-43(a) consists of a UJT and a capacitor (C_{1}) charged via resistance R_{E}. When the capacitor voltage (V_{C}) reaches V_{P} the UJT fires and rapidly discharges C_{1} to V_{EB1(sat)}. The device then cuts off and the capacitor commences charging again. The cycle is repeated continually, generating a sawtooth waveform across C_{1} as illustrated in Fig. 19-43(b). The time (t) for the capacitor to charge from V_{EB1(sat)} to V_{P} may be calculated, and the frequency of the sawtooth determined approximately as 1/t. The discharge time (t_{D}) is difficult to calculate because the UJT is in its negative resistance region and its resistance is changing. However, t_{D} is much less than t, and so it can normally be neglected. Rewriting Eq. 19-6,

Resistor R_{3} in the circuit in Fig. 19-43 is included to produce a spike waveform output, as illustrated. When the UJT fires, the current surge through terminal B_{2} produces the negative-going voltage spike across R_{3}. A resistor could also be included in series with terminal B_{1} to produce positive-going spikes. Both resistor values should be much lower than the R_{BB} for the UJT.

**UJT Control of an SCR:**

Unijunction transistors are frequently employed in SCR and TRIAC control circuits. In the typical circuit shown in Fig. 19-44(a) diode D_{1}, resistor R_{1}, and Zener diode D_{2} provide a low-voltage dc supply to the UJT circuit derived from the positive half-cycle of the ac supply voltage. D_{1} also isolates the UJT Circuit Diagram during the supply negative half-cycle. Capacitor C_{1} is charged via resistor R_{2} to the UJT firing voltage, and the SCR is triggered by the voltage drop across R_{3}. By adjusting R_{2} the charging rate of C_{1} and the UJT firing time can be selected. The waveforms in Fig. 19-44(b) show that 180Â° of SCR phase control is possible.