**Single Stage Common Emitter Amplifier Circuit:**

Specification – Bias circuit design for the Single Stage Common Emitter Amplifier Circuit in shown in Fig. 12-1 and ac analysis of the circuit is already explained. Design of this circuit (or any other circuit) normally commences with a specification which might list: the supply voltage, minimum voltage gain, frequency response, signal source impedance, and the load impedance.

**Selection of I**_{C}, R_{C}, and R_{E}

_{C}, R

_{C}, and R

_{E}

Designing for a particular voltage gain requires the use of ac negative feedback to stabilize the gain. The circuit shown in Fig. 12-1 has no provision for negative feedback, consequently, it is designed to achieve the largest possible voltage gain. From Eq. 6-15, the voltage gain of a Single Stage Common Emitter Amplifier Circuit,

Because A_{v} is directly proportional to R_{C}||R_{L},Â design for the greatest voltage gain would seem to require selection of the largest possible collector resistance. However, a very large value of R_{C}Â might make the collector current too small for satisfactory transistor operation. For most small-signal transistors, I_{C}Â should not be less than 500 Î¼A. A good minimum I_{C}Â to aim for is 1 mA. Special low-noise transistors operate with much lower collector current levels.

The transistor h_{fe} value is related to I_{C}, so I_{C}Â might be selected high to give the largest h_{fe}, again to achieve the greatest A_{v}. But, a high I_{C}Â level results in a small R_{C} value for a given voltage drop (V_{RC}). So, a high I_{C}Â level might actually result in a low A_{v} value, although h_{fe}Â might be relatively large.

For a given level of I_{C},Â the largest possible voltage drop across R_{C} gives the greatest R_{C} value, (R_{C}Â = V_{RC}/I_{C}). To make V_{RC}Â as large as possible, V_{CE} and V_{E} should be held to a minimum, [see Fig. 12-Â2(a)]. The collector-emitter voltage should typically be around 3 V. This is large enough to ensure that the transistor operates linearly, and it also allows for a collector voltage swing of Â±1 V which is usually adequate for a small-signal amplifier. Another consideration in selecting R_{C} is that there is nothing to be gained by making R_{C} larger than R_{L}. In fact, R_{C} should normally be very much smaller than R_{L}, so that R_{L} has little effect on the circuit voltage gain.

For good bias stability, the emitter resistor voltage drop (V_{E}) should be much larger than the base-emitter voltage (V_{BE}). This is because V_{E} = V_{B} – V_{BE}, and when V_{E}Â â‰« V_{BE},Â V_{E} will be only slightly affected by any variation in V_{BE}Â (due to temperature change or other effects). Consequently, I_{E}Â and I_{C}Â remain fairly stable at I_{C} â‰ˆ I_{E} = V_{E}/R_{E}. A minimum V_{E} of 5 V gives good bias stability in most circumstances, [see Fig. 12-2 (a)]. With supply voltages less than 10 V, V_{E} might have to be reduced to 3 V to allow for reasonable levels of V_{CE} and V_{RC}. Normally, an emitter resistor voltage drop less than 3 V is likely to produce poor bias stability.

Once V_{E}, V_{CE}, and I_{C} are selected, V_{RC} is determined as,

Then, R_{C} and R_{E} are calculated,

**Bias Resistors:**

As we know already, selection of the voltage divider current (I_{2}) as I_{C}/10 gives good bias stability and reasonably high input resistance. Where the input resistance is not important, I_{2}Â may be made equal to I_{C}Â for excellent bias stability. The bias resistors are calculated as,

Selecting R_{2} = 10 R_{E} gives I_{2}Â â‰ˆ I_{C}/10,Â [Fig. 12-2(b)]. The precise level of I_{2} can be calculated as I_{2}Â =V_{B}/R_{2},Â and this can be used in the equation for R_{1}.

**Bypass Capacitor:**

All capacitors should be selected to have the smallest possible capacitance value, both to minimize the physical size of the circuit and for economy (large capacitors are the most expensive). Because each capacitor has its highest impedance at the lowest operating frequency, the capacitor values are calculated at the lowest signal frequency that the circuit is required to amplify. This frequency is the circuit lower cutoff frequency, or low 3 dB frequency (f_{1}), (see Fig. 12-3).

Bypass capacitor C_{2} in Fig. 12-1 is normally the largest capacitor in the circuit, so C_{2} is selected to set f_{1} at the desired frequency. Voltage gain was developed for a Single Stage Common Emitter Amplifier Circuit with an unbypassed emitter resistor (R_{E}). Rewriting the equation to include X_{C2}Â in parallel with R_{E} gives

NormallyÂ R_{E}Â â‰« X_{C2}, so R_{E}Â can be omitted. Also, X_{C2}Â is capacitive,

whenÂ h_{fe}Â = (1 + h_{fe}) X_{C2},

Therefore, atÂ f_{1},

AtÂ f_{1},

Equations 12-2 and 12-3 give the smallest value for the bypass capacitor. When selecting a standard value for the capacitor, the next larger value should be chosen. This will give a cutoff frequency slightly lower than theÂ f_{1Â }value used in the calculations.

It is important to note that the emitter bypass capacitor is calculated in terms of the resistance ‘seen looking into’ the transistor emitter terminal (the resistance in series with C_{2}). The capacitor value is not determined in relation to the value of the emitter resistor (R_{E}).

**Coupling Capacitors:**

The coupling capacitors (C_{1} and C_{3} in Fig. 12-1) should have a negligible effect on the frequency response of the circuit. Figure 12-Â6(a) illustrates the fact that X_{C1}Â and Z_{i} constitute a voltage divider If X_{C1} is too large, the circuit ac input voltage (v_{i}) will be significantly smaller than the signal voltage (v_{s}). Similarly, X_{C3} andÂ R_{LÂ }attenuate the ac voltage at the transistor collector, so that the ac output voltage (v_{o}) can be smaller than the ac collector voltage (v_{o}), [Fig. 12-6(b)]. To minimize the effects of C_{1} and C_{3}, the reactance of each coupling capacitor is selected to be approximately equal to one-tenth of the impedance in series with it at the lowest operating frequency for the circuit (f_{1}).

Usually, R_{L}Â â‰« Z_{o},Â and often Z_{i}Â â‰« r_{s},Â so that Z_{o} and r_{s}Â can be omitted in Equations 12-4 and 12-5. Once again, the equations give minimum capacitance values, so that the next larger standard values should always be selected for C_{1} and C_{3}.

Equations 12-4 and 12-5 give an impression that approximately 10% of the signal and output voltages are lost across C_{1} and C_{3}. This would be true if the quantities were resistive. However, X_{C1} and X_{C3} are capacitive while Z_{i} and R_{LÂ }are usually resistive. So, when the actual loss is calculated, it is found to be only around 0.5% for each capacitor.

Another approach to the selection of coupling capacitors is to make X_{C1}Â = Z_{i}Â Â at two octaves below f_{1}.

The output coupling capacitor is then determined by making impedance of C_{3} equal to R_{L} at two octaves below f_{1}/4.

When Equations 12-6 and 12-7 are used to determine the values of the coupling capacitors, it can be shown that the capacitor attenuation effects are less than 5% of A_{v}.

**Shunting Capacitor:**

Sometimes an amplifier is required to have a particular upper cutoff frequency, (f_{2} in Fig. 12-3). The transistor must be selected to have a much higher cutoff frequency than f_{2}. The upper cutoff frequency for the circuit can then be set by connecting a small capacitor from the transistor collector terminal to ground, (C_{4} in Fig. 12-7).