**Single Stage Common Source Amplifier:**

Bias circuit design for the Single Stage Common Source Amplifier in shown in Fig. 12-10. As with the common-emitter BJT circuit, design commences with specification of the supply voltage, amplification, frequency response, load impedance, etc.

**Selection of I**_{D},R_{D}, and R_{s}

_{D},R

_{D}, and R

_{s}

The circuit shown in Fig. 12-10 has no provision for negative feedback, so, it should be designed to achieve the largest possible gain. The voltage gain of a CS circuit is,

Because A_{v} is directly proportional to R_{D}||R_{L}, design for the greatest voltage gain normally requires selection of the largest possible drain resistance. However, a very large value of R_{D} might make the drain current too small for satisfactory FET operation. Also, low I_{D} levels give small Y_{fs} values, which result in lower ac voltage gain. Furthermore, R_{D} should normally be much smaller than R_{L}, so that R_{L} has little effect on the circuit voltage gain.

For a given level of I_{D}, the largest possible voltage drop across R_{D} gives the greatest R_{D} value, (R_{D} = V_{RD}/I_{D}). To make V_{RD} as large as possible, V_{DS} and V_{S} should be held to a minimum, (see Fig. 12-11(a)]. The drain-source voltage should typically be V_{DS(min)} = (V_{P(max)} + 1 V). This is large enough to ensure that the FET operates in the pinch-off region of its characteristics. It also allows for a drain voltage swing of ±1 V, which is usually adequate for a small-signal amplifier. If the gate-source bias voltage (V_{GS}) is other than zero, then, as illustrated in Fig. 12-11(a), the minimum V_{DS} should be calculated as,

Recall from earlier article that for good bias stability, the source resistor voltage drop (V_{S}) should be as large as possible. Where the supply voltage is small, V_{S} may be reduced to a minimum to allow for the minimum level of V_{DS}. A reasonable approach for most FET circuits is to calculate the the sum of V_{S} and V_{RD} from,

and then make,

Once V_{S}, V_{RD}, and I_{D} are selected, R_{D} and R_{S} are calculated,

As already discussed, a bias line should be drawn upon the FET transfer characteristics to determine a suitable gate bias voltage (V_{G}). The selected maximum drain current (I_{D(max)}) is plotted on the maximum transfer characteristics for the FET used. The bias line is then drawn through this point with a slope of 1/R_{s}. The gate bias voltage is read from the intersection of the bias line and the V_{G} scale. As an alternative to drawing the bias line, V_{GS }can be read from the transfer characteristic when I_{D(max)} is plotted. Then,

Instead of using the FET transfer characteristics, V_{P(max)} and I_{DSS(max) }can be substituted to calculate the V_{GS} level.

**Bias Resistors:**

With a voltage divider bias circuit [as in Fig. 12-11(13)], R_{2} is usually selected as 1 MΩ or less. Smaller resistance values may be used where a lower input impedance is acceptable. Larger resistance values may also be used, however, as discussed earlier, there are distinct disadvantages to using resistances higher than 1 MΩ. With R_{2} determined, R_{1} is calculated using R_{2} and the ratio of V_{R1} to V_{R2}.

**Capacitors:**

As for a BJT capacitor-coupled circuit, coupling and bypass capacitors should be selected to have the smallest possible capacitance values. The largest capacitor in the circuit (source bypass capacitor C_{2} in Fig 12-10) sets the circuit low 3 dB frequency (f_{1}). Equation 11-10 was developed for the voltage gain of a Single Stage Common Source Amplifier with an unbypassed source resistor (R_{S}). Rewriting the equation to include X_{C2} in parallel with R_{S} gives

Normally R_{S} ≫ X_{C2}, so R_{S} can be omitted. Also, X_{C2 }is capacitive,

When Y_{fs}X_{C2} =1,

Therefore, at f_{1},

From Section 11-7,

So, at f_{1},

Equations 12-12 gives the smallest value for the source bypass capacitor. When selecting a standard value, the next larger capacitance value should be chosen. This will give a cutoff frequency slightly lower than the f_{1} value used in the calculations.

As explained in earlier, it is important to note that the bypass capacitor is calculated in terms of the resistance seen looking into the device terminal (the resistance in series with C_{2}). The capacitance value is not determined in terms of the parallel resistor (R_{S}).

The input and output coupling capacitors should have almost zero effect on the circuit frequency response. It is explained that X_{C1} in series with Z_{1} and X_{C3} in series with R_{L}, constitute voltage dividers that can attenuate the ac input and output voltages. To minimize the attenuation, the reactance of each coupling capacitor is selected to be approximately one-tenth of the impedance in series with it at the lowest operating frequency for the circuit (f_{1}). Equations 12-4 and 12-5 apply once again for the calculation of the minimum C_{1} and C_{2} values.

As in BJT circuits, R_{L} is usually much larger than Z_{o}, and Z_{i} is often much larger than r_{s}, so Z_{o} and r_{s} can be omitted in Equations 12-4 and 12-5. As always, the equations give minimum capacitance values, so that the next larger standard values should always be selected for C_{1} and C_{3}.