**BJT Power Amplifier with Differential Input Stages:**

Amplifier Circuit – The direct-coupled amplifier in Fig. 18-33 has a BJT Power Amplifier with Differential Input Stages constituted by transistors Q_{1} and Q_{2}. It also has an intermediate stage (Q_{3}) with a constant current load (Q_{4}). Both pairs of output stage transistors (Q_{5} and Q_{7}) and (Q_{6} and Q_{8}) are in quasi-complementary configuration, instead of the usual complementary form. This arrangement helps to minimize the required supply voltage by removing the V_{BE} of the power transistors from the V_{CC} equation.

The BJT Power Amplifier with Differential Input Stages facilitates negative feedback (NFB), and the whole circuit functions like an operation amplifier. Q_{1} base is the noninverting input, Q_{2 }base is the inverting input, and the junction of R_{14} and R_{15} is the output terminal. There is 100% dc NFB provided from the output via R_{6} to Q_{2} base. This keeps the output dc voltage at the same level as Q_{1} base, (at ground). With C_{2} behaving as an ac short-circuit, the ac NFB is divided by R_{5} and R_{6} to give a closed loop gain; A_{CL} = (R_{5} + R_{6})/R_{5}.

Zener diode D_{3} and resistor R_{4} decouple the power supply ripple on the negative supply line. The dynamic impedance of D_{1} combined with R_{4} functions as an ac voltage divider to attenuate the ripple at the emitters of Q_{1} and Q_{2}. Ripple at this point is amplified just like an input signal. Capacitors C_{3} and C_{5} are frequency-compensating components.

**Amplifier Design:**

The design procedure for the output and intermediate stages of the circuit in Fig. 18-33 is similar to procedures already discussed. Design of the BJT Power Amplifier with Differential Input Stages is very simple. The dc collector currents for Q_{1} and Q_{2} should be larger than the peak base current for Q_{3}, and the voltage drop across R_{2} is (V_{E3} + V_{BE3}). Zener voltage V_{Z3} is any convenient level, usually around 0.5 V_{EE}. Resistor R_{3} is calculated to pass I_{E} ≈ (I_{C1} + I_{C2}), and R_{4} must pass (I_{Z} + I_{E}).

Q_{1} bias resistor R_{1} is determined from earlier Equation, R_{6} is selected equal to R_{1}, and R_{5} is calculated in terms of R_{6} to give the desired closed-loop gain. The impedance of C_{2} is made equal to R_{5} at the desired lower cutoff frequency (f_{1}), so that C_{2} sets f_{1}. Capacitors C_{1} and C_{4} are determined in the usual way for capacitors that are not to affect f_{1}. An additional capacitor (C_{6}) might be included to set the upper cutoff frequency (f_{2}); (X_{C6} = R_{6} at f_{2}).