**Dual Input Balanced Output Differential Amplifier:**

The dual input balanced output differential amplifier configuration is shown in Fig. 20.2. In the given circuit two input signals v_{in1} and v_{in2} are applied to the bases B_{1} and B_{2} of transistors Q_{1} and Q_{2}. The differential input under amplification is the difference of the two input signals v_{in1} and v_{in2} and denoted by v_{d}. The output in this configuration is balanced as it is measured between the two collectors C_{1} and C_{2}, which are at the same dc potential w.r.t. ground.

**1. DC Analysis:**

DC analysis of a differential amplifier circuit is done for determination of operating points (I_{CQ} and V_{CEQ}) when no signal is applied (i.e., v_{in1} = v_{in2} = 0). For dc analysis we require a dc equivalent circuit of the differential amplifier. The dc equivalent circuit of the circuit given in Fig. 20.2 is shown in Fig. 20.3 which is obtained by setting v_{in1} = v_{in2} = 0. Since, both the transistors Q_{1} and Q_{2} are identical (matched pair) and also the passive loads (R_{C1} = R_{C2} = R_{C}) are the same, we are to determine Q-point for transistor Q_{1} only. The same Q-point can be used for transistor Q_{2} also.

Applying Kirchhoff’s voltage law to the base-emitter loop of the transistor Q_{1} [Fig. 20.3].

and base current,

Applying Kirchhoff’s current law at node E, we have

Substituting I_{T} = 2I_{E} from Eq. (20.3) and I_{B} = I_{E}/β_{dc} from Eq.(20.2) in Eq. (20.1), we have

where V_{BE} = 0.7 V for silicon transistors and V_{BE} = 0.3 V for germanium transistors.

Usually, R_{i}/β_{dc} << 2R_{E} and , therefore, Eq. (20.4) can be rewritten as

From above Eq. (20.5), we see that the value of R_{E} fixes the emitter current in transistors Q_{1} and Q_{2} for a given value of –V_{EE}. Thus, the desired value of the emitter dc bias current for a given value of –V_{EE} can be obtained by selecting emitter resistance R_{E} of a proper value. Thus, we see that emitter current in transistors Q_{1} and Q_{2} is independent of collector resistance R_{C}.

The voltage at the emitter of transistor Q_{1} is approximately equal to –V_{BE} if the voltage drop across R_{i} is assumed to be negligibly small. Knowing the value of emitter current I_{E} from Eq. (20.5), the voltage at the collector, V_{C} can be determined from the following equation

and collector-to-emitter voltage,

Hence for both transistors I_{CQ} and V_{CEQ} can be determined by using Eqs. (20.4) and (20.6) respectively, because at the Q-point, I_{E} = I_{CQ} and V_{CE} = V_{CEQ}.

The noteworthy point is that the dc analysis Eqs. (20.4) and (20.6) are applicable to all four differential amplifier configurations as long as the biasing arrangement (as discussed above) is the same for each of them.

**2. AC Analysis:**

The expressions for the differential voltage gain A_{d}, common mode gain A_{cm }and the input resistance R_{in} can be derived from ac analysis of the dual input balanced output differential amplifier.

For ac analysis of the differential amplifier shown in Fig. 20.2, the dc voltages +V_{CC} and –V_{EE} are set at zero and small signal T-equivalent models are substituted for the transistors Q_{1} and Q_{2}, as shown in Fig. 20.4 (a).

The noteworthy points about the circuit given in Fig. 20.4(a) are as follows:

- Emitter currents I
_{E1}and I_{E2}are equal, so r′_{e1}= r′_{e2}. That is why, the dynamic or ac emitter resistance of transistors Q_{1}and Q_{2}is simply denoted by r′_{e.} - The voltage across each collector resistor is shown to have a phase difference of 180° (i.e., in phase opposition) with respect to input voltages v
_{in1}and v_{in2}. The polarity assignment is according to the CE configuration, the differential amplifier being basically constructed in CE configuration using two identical CE circuits. - The polarity of the output voltage v
_{out }indicates that the voltage at collector C_{2}is assumed to be more positive with respect to that of collector C_{1}, even though both of them are negative w.r.t. ground.

**(i) Voltage Gain:** Applying KVL to loops I and II of the circuit given in Fig. 20.4 (a), we have

Substituting i_{b1} = i_{e1}/β_{ac} and i_{b2} = i_{e2}/β_{ac }in above equations, we have

Usually R_{i1}/β_{ac} and R_{i2}/β_{ac}, being very small, are neglected and, therefore, the above equations become as follows:

Solving above Eqs. (20.9) and (20.10) for currents i_{e1} and i_{e2}, we have

The output voltage is given by

Substituting the values of i_{e1} and i_{e2} from Eqs. (20.11) and (20.12) in above equation, we have

Above Eq. (20.14) shows that a differential amplifier amplifies the difference of two input signals as expected. The input and output waveforms of the dual input balanced output differential amplifier are depicted in Fig. 20.4 (b).

By defining v_{in1} – v_{in2} = v_{d }as the difference in input voltages, the voltage gain equation for the dual input balanced output differential amplifier is given by

Above Eq. (20.15) reveals that the voltage-gain equation for the differential amplifier is independent of emitter resistance R_{E} and this equation is identical to the voltage-gain equation of the CE amplifier.

**(ii) Differential Input Resistance:** Differential input resistance seen from the signal source is defined as the equivalent resistance that would be measured at either input terminals with the other terminal grounded. Usually source resistances R_{i1} and R_{i2}_{ }are negligibly small and, therefore, will be ignored in the derivation of input resistances R_{in1} and R_{in2} seen seen from the input signal sources v_{in1} and v_{in2} respectively.

The input resistance R_{in1} seen from the input signal source v_{in1} is determined by setting signal source v_{in2} at zero and is expressed in equation form as

Substituting the value of i_{e1} from Eq. (20.11) in above equation, we have

Usually, R_{E} >> r’_{e} which implies that (r′_{e} + 2R_{E}) ≡ 2R_{E} and (r′_{e} + R_{E}) ≡ R_{E} and, therefore, above equation becomes

Similarly, the input resistance R_{in2} seen from the input signal v_{in2} is determined with the signal source v_{in1} set at zero and is expressed in equation form as

Substituting the value of i_{e2} from Eq. (20.12) in above equation, we have

However, (2R_{E} + r′) ≡ 2R_{E} and (R_{E} + r_{e}) = R_{E} since r′_{e} << R_{E} and, therefore, the above equation for R_{in2 }becomes as

**(iii) Output Resistance:** The output resistance may be defined as the equivalent resistance measured at either output terminal with respect to ground. Hence, the output resistance R_{out1} measured between collector C_{1} and ground is equal to collector resistance R_{C} [Fig. 20.4 (a)] i.e., R_{out1} = R_{C}.

Similarly, the output resistance R_{out2} measured between collector C_{2} and ground is equal to collector resistance R_{C} i.e., R_{out1} = R_{C}.

**3. Noninverting and Inverting Inputs:**

In the differential amplifier circuit shown in Fig. 20.2, the input voltage v_{in1 }is referred to as a **noninverting input** as a positive voltage v_{in1} acting alone provides a positive output voltage. This is obvious from voltage-gain Eq. (20.14). Similarly, the positive voltage v_{in2} acting alone produces a negative output voltage, and therefore, v_{in2 }is referred to as a **inverting input** [Eq. (20.14)]. Consequently, the base terminal B_{1} to which v_{in1} is impressed is known as the **noninverting input terminal**, and the base terminal to which v_{in2} is applied is known as the **inverting input terminal**. Noninverting input terminal is marked with plus (+) sign and inverting input terminal is marked with minus (-) sign.

**4. Common-Mode Voltage Gain:**

If in-phase signals v_{in} are applied to each base of the differential amplifier, as depicted in Fig. 20.5(a), the input signal is referred to as **common-mode signal** v_{cm}. Ideally, there will be no ac output voltage with a common-mode input signal because the voltage between the bases is zero. However, due to imperfections within the differential amplifier there will be a small ac output voltage.

In Fig. 20.5(a) equal voltages are applied to the two inputs. A differential amplifier is never used deliberately in this way because the output voltage would be ideally zero. Then what is the need of discussing such a circuit. This is because most static, interference, and other kinds of undesirable pickups are common mode signals.

Because the differential amplifier is a symmetrical circuit, emitter resistance R_{E} can be split into two parallel resistors, as illustrated in Fig. 20.5 (b). Because of symmetry of the circuit, lead connecting the two emitters E_{1} and E_{2} carries no current i.e., i_{x }= 0 because emitters E_{1} and E_{2} are at the same potential.

With i_{x} = 0, connection between two emitters can be eliminated and the resulting independent half circuits are shown in Fig. 20.5 (c). The common-mode behavior can be determined from only one-half of the circuit.

Using r-parameters, the common model for one half of the circuit is depicted in Fig. 20.5 (d).

Referring to Fig. 20.5 (d), we have

The common-mode output voltage is, therefore,

The common-mode voltage gain A_{cm} is, therefore,

**5. Common-Mode Input Resistance R**_{in}_{ cm}

_{in}

_{ cm}

Common-mode input resistance is obtained as under:

Common mode input resistance,

**6. Common-Mode Rejection Ratio (CMRR)**

Having defined differential voltage gain A_{d} and common mode voltage gain A_{cm}, a value of the common-mode rejection ratio (CMRR) can be calculated from the following equation

i.e., CMRR may be defined as the ratio of differential voltage gain to common-mode voltage gain.

If a differential amplifier is perfect, CMRR would be infinite because in that case common-mode voltage gain A_{cm} would be zero.

The value of CMRR can also be expressed in logarithmic terms as

Data sheets usually list the values of A_{d} and CMRR’, but not the value of A_{cm}. However, the value of A_{cm} can be determined from the following equation