Programmable Array Logic:
We have seen that PLA device with a Programmable AND array and Programmable OR array. However, Programmable Array Logic programmable logic device with a fixed OR array and a programmable AND array. Because only AND gates are programmable , the PAL is easier to program, but is not as flexible as the PLA. Fig.3.106 shows the array logic of a typical PAL. It has four
inputs and four outputs. Each input has buffer and an inverter gate. It is important to note that two gates are shown with one composite graphic symbol with normal and complement outputs. There are four sections. Each section has three programmable AND gates and one fixed OR gate. The output of section 1 is connected to a buffer-inverter gate and then fedback into the inputs of the AND gates, through fuses. This allows the logic designer to feed an output function back as an input variable to create a new function. Such PALs are referred to as Programmable I/O PALs.
The commercial Programmable Array Logic devices has more gates than the one shown in Fig. 3.105. A typical PAL integrated circuit may have eight inputs, eight outputs, and eight sections, each consisting of an eight wide AND-OR array.
The PAL device discussed in the previous section does not contain any memory elements. Such PALs are useful to implement combinational logic circuits. Hence, Programmable Array Logic devices which do not contain any memory elements such as flip-flops are called combinational PALs.
Some PALs have flip-flops at the output. The flip-flops store the output. The several flip-flops at the output form a register and because these outputs have tri-state buffers, the output of register can be controlled. Such PALs are referred to as registered PALs. Refer Fig. 3.110. As shown in the Fig. 3.110, the flip-flop outputs are made available as an input to be used in the generation of additional product terms. This feedback feature allows PALs to be used to design counters, registers, and sequential controllers.
In recent years, configurable (sometimes called generic) device architectures have become extremely popular. These devices simplify procurement, qualification and inventory requirements by replacing a large number of simpler Programmable Array Logic type devices with a “one size fits all” device. In addition, their flexible architectures allow designs to be implemented that are challenging or simply impossible for the simpler PAL devices to handle.
This architectural flexibility is provided by equipping the device with a variety of configuration fuses separate from those found in the programmable AND array. The 22V10 is one such device, and was designed by AMD to be a replacement for all of the 24-pin PALs. To meet this requirement, the 22V10 was de’signed with configurable outputs. These outputs are enhanced with special circuitry called output macrocells. Output macrocells are found on ten of the 22V10’s pins, as shown in Fig. 3.119.
The 22V10 has a total of twelve dedicated inputs, one of which (pin 1) also functions as the common clock input to the edge-triggered D-type flip-flop of each output macrocell. Any of the 22V10’s ten output pins can be used as inputs, so the device is capable of supporting applications requiring up to 22 inputs (of course, if you use all ten I/O pins as dedicated inputs, there is no way to observe the results of your efforts, since there will be no output pins left).
We will examine the structure of the individual output macrocells momentarily, but first, notice that the number of product terms available to the various OR gates in the device differs. The OR gate associated with pins 18 and 19, in fact, have sixteen product terms each available. This means that logic functions of significantly more complexity can be implemented in the 22V10. Fig. 3.112 illustrates the 22V10 in block diagram form.
As mentioned earlier the 22V10 has ten output macrocells, all of which are identical. Fig. 3.113 shows the construction of one of these output macrocells. Each macrocell contains a positive edge-triggered D-type flip-flop and a three configurable multiplexers. The two fuses So and Si that control the multiplexers can be configured in four different ways, as shown in Fig. 3.114. The Fig. 3.114 does not show the fuse interconnections multiplexers and pull-up resistors. But it shows the effective circuit at various combinations of So and Si fuses. From the Fig. 3.114 we can observed that this configurable Programmable Array Logic can be used as registered PAL or combinationed PAL with inverted or non-inverted outputs.
Generic Array Logic Devices:
Another example of a configurable PAL is the Lattice GAL (generic array logic) device. These devices are intended as pin-for-pin replacements for a wide variety of PAL devices. The GAL device, in fact, is designed to be compatible all the way to the fuse level-JEDEC format files. Therefore, virtually any simpler PAL can be directly implemented in the GAL device.
The major distinction between the GAL device and the original 22V10 is the fact that the GAL is electrically erasable. This makes the GAL particularly well suited for engineering prototype activities. The GAL comes in two basic versions. The GAL 16V8 device replaces most 20-pin PAL devices, while the 20V8 replaces most 24-pin PAL, devices. The 16V8 device is shown in Fig. 3.115.
Like the 22V10, the GAL devices utilize a configurable output macrocell. Although the function of the GAL macrocell is similar to the 22V10, the GAL macrocell differs from that of the 22V10 in a number of areas. The GAL macrocell (which Lattice refers to as an output logic macrocell, or OLMC) is shown in Fig. 3.116. For simplicity the fuse interconnections to select the configuration and pullup resistors are not shown in Fig. 3.116.
combinational and registered outputs in devices like the 16R4. The control fuses for the GAL macrocells allow each macrocell to be configured in one of three basic configurations. These configurations correspond the various types of I/O configurations found in the Programmable Array Logic devices that the GAL is designed to replace. Refer Fig. 3.117.
- In the registered Programmable Array Logic mode, each of the 16V8’s eight outputs can be registered or combinational. Those outputs that are configured with registers have eight product terms and a fixed enable input (from pin 11), while those that are combinational have seven product terms with a controlled output Clocking in this mode is from pin 1, which can not be used as an input to the logic array.
- In the combinational mode, the clock and enable inputs (pins 1 and 11) are made available as array inputs. In this mode, output pins 12 and 19 are not available for use as inputs to the array. The combinational mode is intended for emulation of the 16L8-type combinational PALs.
- In the GAL’s third mode (simple mode), there are eight product terms available to each of the eight outputs and no output enable feature is provided (output is always enabled). This mode is intended for emulation of the simple PAL-type devices.
Still another family of devices that are intended as Programmable Array Logic replacements are the PEEL devices from International CMOS Technology. The PEEL 18CV8, shown in Fig. 3.118, features output macrocells that can be configured in any of twelve different ways.
The PEEL output macrocell is illustrated in Fig. 3.119.
The PEEL’s macrocells provide a wider selection of feedback options than do the GAL’s. Notice that there are four fuses used to select the macrocell configuration. The Fig.3.120 shows the twelve different configurations possible for each macrocell using these fuses.
PALs also are available with EX-OR excitation inputs to the output flip-flop. This allows logic reduction when the flip-flop excitation functions are more easily realized using EX-ORs. Fig. 3.121 shows the EX-OR registered output Programmable Array Logic.
We have already seen that XOR gates are used to implement fuse configurable output polarity. XORs have other applications as well. Fig. 3.122 is the logic diagram for the 20X8 device.
In the device, flip-flop input is driven by XOR gate. Each of these XOR gates is fed in turn by two sum-of-products arrays of two product terms each. These XORs can be used to reduce the amount of logic required for many applications, particularly counters. The XORs not only allow dynamic polarity control of the outputs, but also allow surprisingly complex designs to be implemented using very few product terms. In recent years, the value of these extra gates has become increasingly apparent to circuit designers.
The PLDs such as ROM, PALS, PALs and other similar type of devices discussed so far are simple PLDs or SPLDs.