**PLL Frequency Synthesizer Block Diagram:**

The PLL can be used as the basis for frequency synthesizer that can produce a precise series of frequencies that are derived from a stable crystal controlled oscillator.

The Fig. 2.130 shows the Frequency Synthesizer Block Diagram. It is similar to frequency multiplier circuit except that divided by M network is added at the input of phase lock loop.

The frequency of the crystal-controlled oscillator is divided by an integer factor M by divider network to produce a frequency f_{osc}/M

**where **

**f**_{osc}is the frequency of the crystal controlled oscillator.

The VCO frequency f_{VCO} is similarly divided by factor N by divider network to give frequency equal to f_{vco} /N. When the PLL is locked in on the divided-down oscillator frequency, we will have f_{osc}/M = f_{vco}/N, so that f_{vco}=(N/M)f_{osc}.

By adjusting divider counts to desired values large number of frequencies can be produced, all derived from the crystal controlled oscillator.