When the output of the sequential circuit depends on both the present state of flip-flop(s) and on the input(s), the sequential circuit is referred to as Mealy circuit. Fig. 3.39 shows the sample Mealy circuits. As shown in the Fig. 3.39, the output of the circuit is derived from the combination of present state
Looking at Fig. 3.39, we can easily realise that, changes in the input within the clock pulses can not affect the state of the flip-flop. However, they can affect the output of the circuit. Due to this, if the input variations are not synchronized with the clock, the derived output will also not be synchronized with the clock and we get false output (as it is a synchronous sequential circuit). The false outputs can be eliminated by allowing input to change only at the active transition of the clock (in our example HIGH-to-LOW).
In general form the Mealy circuit can be represented with its block schematic as shown in Fig.3.40.