Electronics Engineering Multiple Choice Questions and Answers (MCQs) Part 8:
306. 2-to-1 line multiplexer can be realized using
(a) 1 NAND, 2 OR and 1 NOT gates.
(b) 2 NAND, 2 OR and 1 NOT gates.
(c) 2 NAND, 1 OR and 2 NOT gates.
(d) 2 NAND, 1 OR and 1 NOT gates.
Answer : (c) 2 NAND, 1 OR and 2 NOT gates.
307. It is required to construct a 2n-to-1 multiplexer by using 2-to-1 multiplexer only. How many of 2-to-1 multiplexers are needed ?
(a) n
(b) 22n
(c) 2n-1
(d) 2n – 1
Answer : (d) 2n – 1
308. An R-S latch is a
(a) combinational circuit.
(b) synchronous circuit.
(c) one bit memory element.
(d) one clock delay element.
Answer : (c) one bit memory element.
309. A J-K flip-flop can be made from an S-R flip-flop by using two additional
(a) NAND gates.
(b) OR gates.
(c) NOT gates.
(d) NOR gates.
Answer : (a) NAND gates.
310. A T-flip-flop function is obtained from a JK flip-flop. If the flip-flop belongs to a TTL family, the connection needed at the input must be
(a) J=K=1
(b) J=K=0
(c) J=1 and K=0
(d) J=0 and K=1+
Answer : (a) J=K=1
311. What is the other name of a Johnson counter?
(a) Ring counter.
(b) Ripple counter.
(c) Up-down counter.
(d) Twisted ring counter.
Answer : (d) Twisted ring counter.
312. A 4-bit module-16 ripple counter uses J-K flip-flop. If the propagation delay of each flip-flop is 50 ns, the maximum clock frequency that can be used is equal to
(a) 20 MHz.
(b) 10 MHz.
(c) 8 MHz.
(d) 5 MHz.
Answer : (d) 5 MHz.
313. The maximum possible number of states in a ripple counter with 5 flip-flops is
(a) 32
(b) 15
(c) 10
(d) 5
Answer : (a) 32
314. The number of flip-flops required for a MOD-10 ring counter is
(a) 4
(b) 10
(c) 5
(d) None of these
Answer : (a) 4
315. Which family has the better noise margin?
(a) ECL
(b) DTL
(c) MOS
(d) TTL
Answer : (c) MOS
316. Which one of the following is not a characteristic of RTL logic families?
(a) High switching speed.
(b) Poor noise immunity.
(c) Low power dissipation.
(d) Fan out is 5.
Answer : (a) High switching speed.
317. The noise margin of a TTL gate is about
(a) 0.2 V
(b) 0.4 V
(c) 0.6 V
(d) 0.8 V
Answer : (b) 0.4 V
318. While ________ is the fastest unsaturated logic gate _________ has the excellent noise immunity.
(a) ECL, TTL
(b) TTL, ECL
(c) ECL, HTL
(d ) RTL, DTL
Answer : (c) ECL, HTL
319. In the CMOS inverter, the power dissipation is
(a) low only when VIN is low.
(b) low only when VIN is high.
(c) high during dynamic operation.
(d) low during dynamic operation.
Answer : (d) low during dynamic operation.
320. Which one of the following is not a characteristic of CMOS configuration ?
(a) CMOS devices dissipate much lower static power than bipolar devices.
(b) CMOS devices have low input impedances.
(c) CMOS devices have higher noise margins.
(d) CMOS devices have much lower transconductance than bipolar devices.
Answer : (b) CMOS devices have low input impedances.
321. Which of the following output configurations are available in a TTL gate ?
1. Open collector output.
2. Totem-pole output.
3. Tristate output.
Select the correct answer from the codes given below :
(a) 1 only.
(b) 1 and 2 only.
(c) 2 and 3 only.
(d) 1, 2, and 3.
Answer : (d) 1, 2, and 3.
322. The voltage resolution for an n-stage ladder network is given as
(a) VREF/2n+1
(b) VREF/2n
(c) VREF/2n-1
(d) VREF/n-1
Answer : (b) VREF/2n
323. How many bits will a D/A converter use so that its full-scale output voltage is 5 V and its resolution is at the most 10 mV?
(a) 5
(b) 7
(c) 9
(d) 11
Answer : (c) 9
324. An 8-bit converter is used for a dc range of 0-10 V. Find the weight of LSB.
(a) 39 mV.
(b) 78 mV.
(c) 39.2 mV.
(d) 40 mV.
Answer : (a) 39 mV.
325. The fastest A/D converter is
(a) flash type.
(b) SAR type.
(c) dual slope type.
(d) None of the above.
Answer : (a) flash type.
326. A dual-slope ADC uses an N-bit counter. When the input signal Va is being integrated, the counter is allowed to count up to a value
(a) equal to 2N-2.
(b) equal 2N-1.
(c) proportional to Va.
(d) inversely proportional to Va.
Answer : (c) proportional to Va.
327. The value of n for the n-bit A/D converter required to convert an analog input in the range of 0 to 5 volts to an accuracy of 10 mV is
(a) 8
(b) 9
(c) 7
(d) 6
Answer : (b) 9
328. An 8-bit, unipolar Successive Approximation Register type ADC is used to convert 3.5 V to digital equivalent output. The reference voltage is +5 V. The output of the ADC, at the end of 3rd clock pulse after the start of conversion, is
(a) 1010 0000
(b) 1000 0000
(c) 0000 0001
(d) 0000 0011
Answer : (a) 1010 0000
329. A 12-bit ADC is operating with a 1 µs clock period and total conversion time is seen to be 14 µs. The ADC must be of
(a) flash type.
(b) counting type.
(c) integrating type.
(d) successive approximation type.
Answer : (d) successive approximation type.
330. Which of the following is NOT true for a digital frequency counter?
(a) High accuracy.
(b) Less costly.
(c) Wide range of frequency measurement.
(d) Accepts input in the form of train of pulses.
Answer : (b) Less costly.
331. The output frequency of a decade counter that is clocked from a 50 kHz signal is
(a) 12.5 kHz
(b) 50 kHz
(c) 5 kHz
(d) 500 kHz
Answer : (c) 5 kHz
332. Personal computer cannot be used for which one of the following?
(a) Game playing.
(b) Weather forecasting.
(c) Office automation.
(d) Home computing.
Answer : (b) Weather forecasting.
333. A microprocessor is ALU
(a) and control unit on a single chip.
(b) and memory on a single chip.
(c) register unit and I/O device on a single chip.
(d) register unit and control unit on a single chip.
Answer : (d) register unit and control unit on a single chip.
334. ALU (Arithmetic Logic Unit) of an 8085 microprocessor consists of:
(a) Accumulator, temporary register, arithmetic and logic circuits.
(b) Accumulator, arithmetic, logic circuits and five flags.
(c) Accumulator, arithmetic and logic circuits.
(d) Accumulator, temporary register, arithmetic, logic circuits and five flags.
Answer : (d) Accumulator, temporary register, arithmetic, logic circuits and five flags.
335. Consider the following statements:
In 8085 microprocessor, data-bus and address-bus are multiplexed in order to
1. Increase the speed of microprocessor.
2. Reduce the number of pins.
3. Connect more peripheral chips.
Which of the above statements is/are correct?
(a) 1 only
(b) 2 only
(c) 2 and 3
(d) 1, 2 and 3
Answer : (b) 2 only
336. Consider the following statements:
1. The output unit of a computer communicate the response of the computer to the user.
2. READ/WRITE memory is volatile.
3. The flip-flops in a register are connected in parallel.
Which of the above statements is/are correct?
(a) 1 only
(b) 1 and 2
(c) 2 and 3
(d) 3 only
Answer : (b) 1 and 2
337. Consider the following statements regarding registers and latches:
1. Registers are temporary storage devices, whereas latches are not.
2. A latch employs cross-coupled feedback connections.
3. A register stores a binary word, whereas a latch does not.
The correct statement(s) is/are
(a) 1 only.
(b) 2 only.
(c) 1 and 3.
(d) 2 and 3.
Answer : (d) 2 and 3.
338. A pulse train can be delayed by a finite number of clock periods using
(a) a serial-in serial-out shift register.
(b) a serial-in parallel-out shift register.
(c) a parallel-in serial-out shift register.
(d) a parallel-in parallel-out shift register.
Answer : (b) a serial-in parallel-out shift register.
339. A bus organized processor consists of 15 registers. The number of selection lines in each multiplexer and in the destination decoder are respectively
(a) 2 and 4.
(b) 4 and 2.
(c) 4 and 4.
(d) 4 and 8.
Answer : (c) 4 and 4.
340. In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively.
(a) B and F
(b) A and F
(c) H and F
(d) A and C
Answer : (b) A and F
341. To total number of 1’s in a 15-bit shift register is to be counted by clocking into a counter which is preset to 0. The counter must have which one of the following?
(a) 4-bits.
(b) 5-bits.
(c) 16-bits.
(d) 5-bits.
Answer : (a) 4-bits.
342. A PLA can be used
(a) as a microprocessor.
(b) as a dynamic memory.
(c) to realise a sequential logic.
(d) to realise a combinational logic.
Answer : (d) to realise a combinational logic.