In this section, we are going to see supporting circuits such as clock circuit, reset circuit, demultiplexer circuit, and circuit required for generation of control signals. In this section, we are going to see these additional circuits and their operation in connection with Supporting Circuits of 8085 Microprocessor.
The 8085 has on chip clock generator. Fig. 4.1 shows the internal block diagram of the on chip clock generator. The internal clock generator requires tuned circuit like LC, RC or crystal, or external clock source as an input to generate the clock. The internal T-flip flop divides the frequency by 2. Hence the operating frequency of the 8085 is always half of the oscillator frequency.
LC Tuned Circuit :
It is a LC resonant tank circuit. The resonant frequency for this circuit is given by
where Cint is the internal capacitance and it is normally 15 pF. The output frequency of this circuit has 10% variations. To minimize the variations in the output frequency, it is recommended to have Cext at least twice that of Cint i.e. 30 pF.
RC Tuned Circuit : Fig. 4.3 shows the RC tuned circuit. The output frequency of this circuit is also not exactly stable. But this circuit .has an advantage that its component cost is less.
Crystal Oscillator Circuit : Fig. 4.4 shows the crystal oscillator circuit. It is the most stable circuit. The 20 pF capacitor in the circuit is connected to assure oscillator start-up at the correct frequency.
External Clock :
Fig. 4.5 shows how to drive clock input of 8085 with external frequency source. Here external clock is applied at X1 input and X2 input is kept open.
We know that AD0 to AD7 lines are multiplexed and the lower half of address (A0 – A7) is available only during T1 of the machine cycle. This lower half of address is also necessary during T2 and T3 of machine cycle to access specific location in memory or I/O port. This means that the lower half of an address bus must be latched in T1 of the machine cycle, so that it is available throughout the machine cycle. The latching of lower half of an address is done by using external latch and ALE signal from 8085. The Fig. 4.6 shows the hardware connection for latching the lower half of an address. The IC 74LS373 is an 8-bit latch, having 8 D flip-flops. The input is transferred to the output only when clock is high. This clock signal is driven by ALE signal from 8085. The ALE signal is activated only during T1, so input is transferred to the output only during T1 i.e. address (A0 – A7) on the AD0 to AD7 multiplexed bus. In the remaining part of the machine cycle, ALE signal is disabled so output of the latch (A0 – A7) remains unchanged. To latch lower half of an address, in each machine cycle, the 8085 gives ALE signal high during T1 of every machine cycle.
On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction from address 0000H. For proper reset operation reset signal must be held low for at least 3 clock cycles. The power-on reset circuit can be used to ensure execution of first instruction from address 0000H. Fig. 4.7 shows the power-on reset circuit with typical R, C values. (Note : R, C values may vary due to power supply ramp up time).
Upon power-up, RESET IN must remain low for at least 10ms after minimum Vcc has been reached, in the circuit shown in Fig. 4.7. Upon power up or key press, the RESET IN goes low and slowly rises to +5V, providing sufficient time for the processor to reset the system. The diode is connected to discharge the capacitor immediately when power supply is switched OFF.
After RESET, 8085 loads 0000H in PC register and clears the INTE flag. Before going to execute interrupt service routine, it is necessary to setup certain parameters, required to execute interrupt service routine. To avoid interrupt to occur before completion of these initial requirements, after power on or reset, INTE flip-flop is cleared to disable interrupts. It can be enabled by EI instruction after initial settings.
As we know that, after power up or reset 8085 fetches its first instruction from 0000H address, and it has to be the first instruction from monitor program. Therefore EPROM consisting of monitor program must be located from address 0000H in any Supporting Circuits of 8085 Microprocessor.
Generation of Control Signals:
The Supporting Circuits of 8085 Microprocessor provides RD and WR signals to initiate read or write cycle. Because these signals are used both for reading/writing memory and for reading/writing an input device, it is necessary to generate separate read and write signals for memory and I/O devices.
The 8085 provides IO/M signal to indicate whether the initiated cycle is for I/O device or for memory device. Using IO/M signal along with RD and WR, it is possible to generate separate four control signals :
Fig. 4.8 shows the circuit which generates MEMR, MEMW, IOR and IOW signals.
We know that for OR gate, when both the inputs are low then only output is low. Table 4.1 shows the truth table used to generate MEMR, MEMW, IOR and IOW signals. The signal IO/M goes low for memory operation. This signal is logicallLORed with RD and WR to get MEMR and MEMW signals. When both RD and IO/M signals go low, MEMR signal goes low. Similarly, when both WR and IO/F/11 signals go low, MEMW signal goes low. To generate IOR and IOW signals for I/O operation, IO/M signal is first inverted and then logically ORed with RD and WR signals.
Typically, the 8085 buses can source 400 μA and sink 2 mA of current, i.e. it can drive only one TTL load. Therefore, it is necessary to increase driving capacity of the 8085 buses. Bus drivers, buffers are used to increase the driving capacity of the buses.
Unidirectional Buffers :
As we know, the address bus is unidirectional, 8-bit unidirectional buffer, 74LS244 is used to buffer higher address bus. The Fig. 4.10 shows the logic diagram of 74LS244. It consists of eight non-inverting buffers with tri-state outputs. Each one can sink 24 mA and source 15 mA of current. These buffers are divided into two groups. The enabling and disabling of these groups are controlled by 1G and 2G lines.
Bi-directional Buffer :
To increase the driving capacity of data bus, bi-directional buffer is used. Fig. 4.11 shows the logic diagram of the bi-directional buffer 74LS245, also called an octal bus transceivers. It consists of sixteen non-inverting buffers, eight for each direction, with tri-state output. The direction of data flow is controlled by the pin DIR. When DIR is high, data flows from the A bus to the B bus; when it is low, data flows from B to A. The active low enable signal and the DIR signal are ANDed to activate the bus lines. Each buffer in this device can sink 24 mA and source 15 mA of current.
Fig. 4.12 shows schematic of the Supporting Circuits of 8085 Microprocessor demultiplexed address bus and control signals.
It also shows clock and reset circuits. Interrupt lines which are not in use are grounded. This is necessary because floating interrupt line may cause false triggering of interrupt. Similarly, since the DMA controller is not used, HOLD line is also grounded. As we know READY signal is used to synchronize slow peripherals with the Supporting Circuits of 8085 Microprocessor. When it is low, microprocessor enters in the wait state and when it is high, it indicates that the memory or peripheral is ready to send or receive data. Here, the READY signal is tied high to prevent the microprocessor from entering the wait state ALE signal is connected to the clock input of the latch, to latch the low order address in T1 of the machine cycle. To control the direction of the bi-directional buffer 74LS245, RD signal from 8085 is connected to DIR input of the bi-directional buffer. Thus, when RD signal is low, DIR is low and data flows from memory or I/O device to the microprocessor, performing read operation. When RD signal is high, DIR is high and data flows from Supporting Circuits of 8085 Microprocessor to memory or I/O device performing write operation.