**Parallel Current Negative Feedback Circuit:**

**Current Feedback Circuit –** In series-voltage feedback, a portion of the output voltage is fed back in series with the signal source. In Parallel Current Negative Feedback Circuit, a portion of the output current is fed back in parallel with the signal source. Just as series voltage feedback stabilizes the voltage gain of a circuit, so parallel current feedback stabilizes the current gain.

Consider the do feedback pair circuit in Fig. 13-29. An unbypassed resistor (R_{F2}) is connected in the emitter circuit of transistor Q_{2}, and Q_{1} bias resistor (R_{F1}) is connected at the emitter terminal of Q_{2}. With this arrangement, any ac voltage developed across R_{F2} is applied to R_{F1}.

Look at the instantaneous polarities of the input voltage (v_{i}) and feedback voltage (v_{f}), as illustrated in the ac equivalent circuit in Fig. 13-30. When v_{i} is moving in a positive direction, v_{c1} is negative-going. Because the emitter of Q_{2} follows the voltage (v_{c1}) at its base, v_{f} (across R_{F2}) is also negative-going at this time.

Now look at the instantaneous ac current directions indicated in Fig. 13-30. When v_{i} goes positive, the signal current (i_{s}) flows into the circuit, and an input current (i_{i}) flows into the base of Q_{1}, as shown. Because v_{f} goes negative when v_{f} is positive-going, a feedback current (i_{f}) flows in R_{F1} in the direction indicated, (from Q_{1} base toward Q_{2} emitter). Thus, some of the signal current is diverted away from the base of Q_{1}. This means that the output current (i_{c2}) is less than it would be if there was no current feedback, consequently, the circuit current gain is reduced.

**Current Gain:**

To determine the effect of negative feedback on the circuit current gain, first investigate the current gain without feedback, (the open-loop current gain). Suppose that R_{F2} in Fig. 13-30 has a bypass capacitor connected across it, so that there is no negative feedback. Assuming that the resistance of R_{F1} is very much larger than the Q_{1} input impedance (h_{ie1}), virtually all of i_{s} enters the base of Q_{1}, (see Fig. 13-30).

i_{c1} divides between R_{1} and Z_{i2}. Using the current divider equation,

The open-loop current gain is,

Now derive an equation for the current gain with negative feedback. Referring to Fig. 13-30, it is seen that i_{o} (in the emitter circuit of Q_{2}) divides between R_{F1} and R_{F2}, giving

The closed-loop current gain is,

If A_{i}B ≫ 1, then

It is seen that,

**Parallel Current Negative Feedback Circuit stabilizes circuit ****current gain.**

It should be noted that, in the current gain equations, the ac output current is taken as the current in the collector circuit of transistor Q_{2}. How this current divides between a capacitor-coupled external load (R_{L}) and the Q_{2} collector resistor (R_{3}) depends on the values of R_{L} and R_{3}.

**Output and Input Impedances:**

In the circuit shown in Figs. 13-29 and 13-30, the Q_{2} collector resistor (R_{2}) is outside the feedback loop. Therefore, like the case of emitter current feedback, the output impedance of this circuit is largely unaffected by feedback. (It can be shown that the impedance looking into the collector of Q_{2} is increased by current feedback.) So, the circuit output impedance is,

Assuming that R_{F1} ≫ h_{ie1}, the circuit input impedance without feedback is,

As already shown, with negative feedback,

Therefore,

**parallel current negative feedback reduces circuit input impedance by a factor of (1 + A _{i}B).**

Although R_{F1} is a bias resistor, it is also part of the feedback network, so it is not in parallel with the circuit input impedance.

Another way of looking at the circuit input impedance is in terms of the the feedback resistor R_{F1} and the voltage gain of the first stage. It can be shown that,

**Circuit Design:**

As with other negative feedback circuits, design of a Parallel Current Negative Feedback Circuit is approached by first ignoring the ac negative feedback components. Resistors R_{F2} and R_{5} in Fig. 13-29 are calculated as a single emitter resistor (R_{E} = R_{F2 }+ R_{5}) to fulfill the desired dc conditions. Also, R_{F1} is calculated (as for other dc feedback bias circuits) to provide the required base current to Q_{1}. R_{F2} is then calculated from Eq. 13-23. Usually, the resistance of R_{F1} is very large, and this results in a calculated resistance for R_{F2} larger than (R_{F2} + R_{5}). In this case, the base resistor for Q_{1 }should be made up of two resistors one of which is bypassed; see (R_{2} = R_{F1} + R_{7}) in Fig. 13-31. R_{F1} is the unbypassed portion of R_{2}, and this is calculated in relation to R_{F2}.

Bypass capacitor C_{2} (in Fig. 13-31) is calculated to give X_{C2} = R_{F2} at the desired lower cutoff frequency. Because the signal is derived from a current source, the impedance of the input coupling capacitor (C_{1}) at f_{1} should be much smaller than the (normally-high) impedance of the signal source. Capacitor C_{3} is determined by making X_{C3} very much smaller than R_{F1} at f_{1}.