Dynamic RAM stores the data as a charge on the capacitor. Fig.3.77 shows the dynamic RAM cell. A dynamic RAM contains thousands of such memory cells. When COLUMN (Sence) and ROW (Control) lines go high, the MOSFET conducts and charges the capacitor. When the COLUMN and ROW lines go low, the MOSFET opens and the capacitor retains its charge. In this way, it stores 1 bit. Since only a single MOSFET and capacitor are needed, the dynamic RAM contains more memory cells as compared to static RAM per unit area.
The disadvantage of dynamic RAM is that it needs refreshing of charge on the capacitor after every few milliseconds. This complicates the system design, since it requires the extra hardware to control refreshing of dynamic RAMs.
In this type of cell, the transistor acts as a switch. The basic simplified operation is illustrated in Fig. 3.78 As shown in the Fig. 3.78 circuit consists of three tri-state buffers : input buffer, output buffer and refresh buffer. Input and output buffers are enabled and disabled by controlling R/W line. When R/W line is LOW, input buffer is enabled and output buffer is disabled. When R/W line is HIGH, input buffer is disabled and output buffer is enabled. With this basic information let us see the read, write and refresh operations.
To enable write operation R/W line is made LOW which enables input buffer and disables output buffers, as shown in the Fig. 3.78 (a). To write a 1 into the cell, the DIN line is HIGH, and the transistor is turned ON by a HIGH on the ROW line. This allows the capacitor to charge to a positive voltage. When 0 is to be stored, a LOW is applied to the DIN line. The capacitor remains uncharged, or if it is storing a 1, it discharges as indicated in Fig. 3.78 (b). When the ROW line is made LOW, the transistor turns off and disconnects the capacitor from the data line, thus storing the charge (either 1 or 0) on the capacitor.
To read data from the cell, the R/W line friade HIGH, which enables output buffer and disables input buffer. Then ROW line is made HIGH. It turns transistor ON and connects the capacitor to the Dour line through output buffer. This is illustrated in Fig. 3.78 (c).
To enable refresh operation R/W line, ROW line and REFRESH line are made HIGH. This turns ON transistor and connects capacitor to COLUMN line. As R/W is HIGH, output buffer is enabled and the stored data bit is applied to the input of refresh buffer. The enabled refresh buffer then produces a voltage on COLUMN line corresponding to the stored bit and thus replenishing the capacitor as shown in Fig. 3.78 (d).
Comparison Between SRAM and DRAM:
In above discussion we have seen memory organization for ROM and Static RAM. In this organization, data is organized as a single bit data word. However, in most memory ICs the data is organized as eight bit data word. In these ICs eight memory cells are connected in parallel and enabled at a time to read or write eight bit data word. The eight memory cells connected in parallel forms a register and memory is nothing but an array of registers.
Memory Structure and Its Requirements:
As mentioned earlier, read/write memories consist of an array of registers, in which each register has unique address. The size of the memory is N x M as shown in Fig. 3.79 (a) where N is the number of registers and M is the word length, in number of bits.