Two Stage Direct Coupled Common Emitter Amplifier: Figure 12-23 shows Two Stage Direct Coupled Common Emitter Amplifier. This time the second stage is a common collector circuit, or emitter follower. Stage 2 gives the circuit a very low output impedance, but has unity voltage gain Stage 1 still has substantial voltage gain. The design […]
ELECTRONIC DEVICES
Direct Coupled Circuits
Direct Coupled Circuits: For economy, the number of components used in any circuit should be kept to a minimum. The use of direct coupling between stages is one way of eliminating components. Figure 12-20 shows a Direct Coupled Circuits that has the base of transistor Q2 directly coupled to the collector of Q1. Comparing this to […]
Single Stage Common Source Amplifier
Single Stage Common Source Amplifier: Bias circuit design for the Single Stage Common Source Amplifier in shown in Fig. 12-10. As with the common-emitter BJT circuit, design commences with specification of the supply voltage, amplification, frequency response, load impedance, etc. Selection of ID,RD, and Rs The circuit shown in Fig. 12-10 has no provision for […]
Capacitor Coupled Two Stage CE Amplifier
Capacitor Coupled Two Stage CE Amplifier: A Capacitor Coupled Two Stage CE Amplifier circuit is shown in Fig. 12- 15 . Stage-1 is capacitor-coupled (via C3) to the input of Stage-2. The signal is applied to the input of Stage-1, and the load is coupled to the output of Stage-2. The signal is amplified by […]
Single Stage Common Emitter Amplifier Circuit
Single Stage Common Emitter Amplifier Circuit: Specification – Bias circuit design for the Single Stage Common Emitter Amplifier Circuit in shown in Fig. 12-1 and ac analysis of the circuit is already explained. Design of this circuit (or any other circuit) normally commences with a specification which might list: the supply voltage, minimum voltage gain, […]
Frequency Response of FET Amplifier
Frequency Response of FET Amplifier: Low-Frequency Response – The low Frequency Response of FET Amplifier circuits is determined by exactly the same considerations as for BJT circuits. The lower cutoff frequency is normally set by a source bypass capacitor, and it can be affected by coupling capacitors. High Frequency Response: Unlike BJTs, a device cutoff […]
FET and BJT Difference
FET and BJT Difference: FET and BJT Difference (CS, CD, and CG Circuit Comparison) – Table 11-1 compares Zi, Zo and Av for CS, CD, and CG circuits. As already discussed, the CS circuit has voltage gain, high input impedance, high output impedance, and a 180° phase shift from input to output. The CD circuit has high […]
Common Gate Circuit
Common Gate Circuit: The FET Common Gate Circuit (CG) shown in Fig. 11-19 uses voltage divider bias. The ac output is taken from the drain terminal, and an external load (RL) is capacitor-coupled to the drain, exactly as in the case of a common-source circuit. Unlike a CS circuit, the ac input for the CG […]
Common Drain Amplifier Circuit Diagram
Common Drain Amplifier Circuit Diagram: The FET Common Drain Amplifier Circuit Diagram shown in Fig. 11-14 has the output voltage developed across the source resistor (RS). The external load (RL) is capacitor-coupled to the source terminal of the FET, and the gate bias voltage (VG) is derived from VDD by means of voltage divider resistors […]
FET Common Source Amplifier with Unbypassed Source Resistors
FET Common Source Amplifier with Unbypassed Source Resistors: Equivalent Circuit – When an unbypassed source resistor (RS) is present in a FET Common Source Amplifier circuit, as shown in Fig.11-10(a), it also appears in the ac equivalent circuit, [Fig. 11-10(b)]. In the complete equivalent circuit RS must be shown connected between the FET source terminal […]
Common Source Circuit Analysis
Common Source Circuit Analysis: A FET Common Source Circuit Analysis is shown in Fig. 11-6. With the capacitors treated as ac short-circuits, the circuit input terminals are the gate and source, and the output terminals are the drain and the source. So, the source terminal is common to both input and output, and the circuit […]
FET Equivalent Circuit Model
FET Equivalent Circuit Model: The complete FET Equivalent Circuit Model is shown in Fig. 11-5(a). It is seen that tilt source terminal is common to both input and out, so this is a common-source equivalent circuit. Resistor RGS between the gate and source terminals is the resistance of the reverse-biased gate-source junction, and Cgs is […]
Coupling Capacitors
Coupling Capacitors: Coupling Capacitors are required at a circuit input to couple a signal source to the circuit without affecting the bias conditions. Similarly, loads are capacitor-coupled to the circuit output to avoid the change in bias conditions produced by direct coupling. Input and output Coupling Capacitors (C1 and C3) and are shown in the FET circuit […]
Biasing FET Switching Circuits
Biasing FET Switching Circuits: JFET Switching – A Biasing FET Switching Circuits is normally in an off state with zero drain current, or in an on state with a very small drain-source voltage. When the FET is off, there is a drain-source leakage current so small that it can almost always be neglected. When the […]
MOSFET Biasing Circuits
MOSFET Biasing Circuits: DE-MOSFET Bias Circuits – DE-MOSFET bias circuits are similar to JFET bias circuits. Any of the FET bias circuits already discussed can be used to produce a negative VGS level for an n-channel MOSFET Biasing Circuits, or a positive VGS for a p-channel device. In this case, both devices would be operating in […]
Universal Transfer Characteristics for FET
Universal Transfer Characteristics for FET: A Universal Transfer Characteristics for FET is simply a transfer characteristic plotted with IDSS = 1 and VP = 1. Then, instead of the scales being calibrated in milliamps and volts, they are marked as the ratios ID/IDSS and VGS/VP. To construct the Universal Transfer Characteristics for FET, Eq. 9-1 is rewritten, Now, by substituting […]
JFET Biasing Circuits
JFET Biasing Circuits: Use of Plus/Minus Supplies – When plus/minus supply voltages are to be used with a JFET Biasing Circuits, the gate terminal is usually grounded via RG, as illustrated in Fig. 10-40(a). In this case, the circuit is essentially a voltage divider bias circuit with the gate bias voltage equal to the level […]